Device I/O
Device I/O: Signals That Behave
Timers, PWM, ADC sequencing, and DMA handoffs taught as a choreography between code and the pinout.
- Duration
- 7 weeks · 84 lab hours
- Format
- Evening labs + async reviews
- Cohort
- September 2025
- Informational price
- KRW 1,650,000
Program narrative
Translate peripheral chapters into timing diagrams you can defend. Labs progress from GPIO edge cases through timer cascades, ADC oversampling trade-offs, and DMA bursts that stay within bus budgets. You will pair oscilloscope captures with driver decisions so future you can debug without guesswork.
What ships in the syllabus
- PWM dead-time lab with annotated half-bridge captures
- ADC scheduling cards for multi-channel sweeps
- DMA ring buffers with underflow drills
- Pin mux conflict matrix workshop
- Level-shifter experiments for mixed-voltage peripherals
- Noise budgeting worksheet for analog front ends
- Written postmortem template for I/O regressions
Outcomes we can observe
- Diagram timer/DMA interactions for a provided peripheral set
- Tune a PWM profile with measurable ripple targets
- Ship a driver snippet with capture-backed evidence
Noah Im
Firmware mentor specializing in motor drives and measurement integrity.
Cohort murmurs
Quote-first
DMA underflow drill was stressful in a good way — finally understand why our music firmware glitched.
Rina · Controls student
The ADC scheduling cards from Device I/O now live in our Confluence — boring title, useful ritual.
Owen · Hardware team · Seoul · internal feedback